The Cellular Microkernel
Operating System
Cellos is an open-source, high-assurance operating system engineered from the ground up for minimal attack surface, capability-based cellular isolation, multi-silicon independence, and absolute digital sovereignty.
Core Architectural Principles
Four Pillars of Cellos
Why traditional monolithic kernels fail, and how cellular architecture redefines operating system reliability.
Fault Containment
All device drivers, file systems, and network stacks run in isolated user-space cells. A crashed graphics driver or Wi-Fi stack reboots in milliseconds without a single kernel panic.
Capability Security
No ambient authority or root superuser privileges. Every process interacts with system resources exclusively through cryptographically unforgeable, fine-grained capability tokens.
Zero Telemetry
Absolute privacy guaranteed by mathematical boundary enforcement. No identifier beacons, no diagnostic phone-homes, and zero hidden network backdoors in the kernel or base services.
Silicon Neutrality
Native Tier-1 targets for open RISC-V, ARM64, and x86_64 architectures. From low-power IoT microcontrollers to high-throughput multi-core cloud servers.
Architectural Paradigm
Monolithic vs. Cellos Cellular Microkernel
How Cellos decouples complex services into isolated memory-safe capsules.
- Massive Ring-0 Attack Surface: 30+ million lines of code running with unrestricted hardware privileges.
- Single Point of Total Failure: A bug or buffer overflow in a third-party USB driver crashes the entire system (BSOD / Kernel Panic).
- Ambient Authority Vulnerability: Root or kernel exploit grants complete, invisible access to all RAM and persistent storage.
- Opaque Telemetry Pipelines: Inherent network stacks tightly coupled with system layers, enabling unverifiable data exfiltration.
- Minimal Trusted Computing Base (TCB): Only <12,000 lines in Ring 0 (scheduling, IPC, virtual memory mapping). Formally verifiable.
- Instant Self-Healing & Fault Containment: Crashed drivers are re-spawned automatically without disrupting the kernel or other cells.
- Object Capability Access Control: No process can reference any resource without an explicit, non-transferable token.
- Mathematically Isolated Zero Telemetry: Network hardware cells cannot read system memory without explicit crypt-tokens.
Engineering Metrics
Technical Specifications
Real numbers behind Cellos performance and security guarantees.
| METRIC / PROPERTY | CELLOS SPECIFICATION | ARCHITECTURAL DESIGN RATIONALE |
|---|---|---|
| Kernel Model | Asynchronous Capability Microkernel | Zero ambient privileges; event-driven message dispatching |
| Ring-0 Code Footprint | < 12,000 Source Lines of Code | Formal verification ready; audited mathematical correctness |
| IPC Latency | ~42 ns (x86_64) / ~48 ns (ARM64) | Zero-copy memory register passing & capability registers |
| Cold Boot Memory | < 8 MB RAM (Base Microkernel + Core Cells) | Runs flawlessly on embedded RISC-V SBCs to enterprise servers |
| Primary Silicon Targets | RISC-V (RV64GC), ARM64 (AArch64), x86_64 | Complete freedom from proprietary silicon lock-in |
| POSIX Compatibility | Modular User-space Libc Enclave | Run standard CLI tools inside isolated containerized cells |
| Governance & Licensing | 100% Free & Open Source (DXSL Commons) | Perpetually non-profit, royalty-free, public good |
DXSL Ecosystem Synergy
Integrated Sovereign Software Stack
Cellos serves as the foundational operating platform for the DXSL privacy ecosystem.
Buttre IME Cell
The high-performance Vietnamese smart input method runs in a dedicated input cell with zero network capability tokens. Keystrokes physically cannot be broadcast over any network adapter.
Haily Cognitive Cell
DXSL's local AI assistant operates inside a sandboxed cognitive compute cell with strictly audited file-access tokens, processing sensitive documents directly on your CPU/NPU without cloud exposure.
Cellos Native Compositor
A tear-free, memory-isolated display compositor providing secure hardware-accelerated user interfaces, cryptographic window isolation, and zero side-channel frame-buffer sniffing.
Boot in 2 Minutes
Download & Evaluation Images
Test Cellos today in QEMU or flash directly to supported bare-metal silicon boards.
x86_64 Live ISO
UEFI / BIOS hybrid boot image. Test on physical PC workstations or via VirtualBox / VMware / Proxmox.
RISC-V QEMU & VisionFive 2
Optimized for StarFive VisionFive 2 and Milk-V Mars RISC-V development boards, or emulate with QEMU RV64.
ARM64 Raspberry Pi 4 / 5
Direct SD card image for Raspberry Pi 4B, 5, and RK3588 single-board computers with DeviceTree configuration.